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CY7C10612DV33
16-Mbit (1 M x 16) Static RAM
Features
Functional Description
The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, take Chip Enables (CE) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C10612DV33 is available in a 54-Pin TSOP II package with center power and ground (revolutionary) pinout.
High speed tAA = 10 ns Low active power ICC = 175 mA at 10 ns Low CMOS standby power ISB2 = 25 mA Operating voltages of 3.3 0.3 V 2.0 V data retention Automatic Power-down when deselected TTL compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 54-pin TSOP II package

Logic Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
SENSE AMPS
1M x 16 ARRAY
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19
BHE WE CE OE BLE
Cypress Semiconductor Corporation Document Number: 001-49315 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 17, 2011
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CY7C10612DV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 175 25 Unit ns mA mA
Pin Configuration
Figure 1. 54-Pin TSOP II (Top View) [1]
I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE NC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4
Note 1. NC pins are not connected on the die.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
DC Input Voltage [2] ............................. -0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................> 2001 V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... -65 C to +150 C Ambient Temperature with Power Applied .......................................... -55 C to +125 C Supply Voltage on VCC Relative to GND [2] ..-0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................. -0.5 V to VCC + 0.5 V
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C VCC 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range -10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage
[2]
Test Conditions Min VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA 2.0 -0.3 GND VI VCC GND VOUT VCC, Output disabled Max VCC, CE VIH, VIN VIH or VIN VIL, f = fMAX Max VCC, CE VCC - 0.3 V, VIN VCC - 0.3 V, or VIN 0.3 V, f = 0 -1 -1 2.4 0.4 VCC + 0.3 0.8 +1 +1 175 30 25 Max
Unit V V V V A A mA mA mA
Input leakage current Output leakage current
VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Automatic CE power-down current -- TTL inputs Automatic CE power-down current --CMOS Inputs
Note 2. VIL (min) = -2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3 V TSOP II 6 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board TSOP II 24.18 5.40 Unit C/W C/W
The AC Test Loads and Waveforms diagram follows. [3] Figure 2. AC Test Loads and Waveforms
50 OUTPUT Z0 = 50
(a)
* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT
ALL INPUT PULSES 3.0 V GND 90% 10%
VTH = 1.5 V 30 pF*
HIGH-Z CHARACTERISTICS: R1 317 3.3 V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b)
90% 10%
R2 351
RISE TIME: > 1 V/ns
(c)
FALL TIME: > 1 V/ns
Note 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
AC Switching Characteristics
Over the Operating Range [4] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
[8, 9]
Description
-10 Min 100 10 10 3 10 5 1 5 3 5 0 Max
Unit
VCC(Typical) to the First Access [5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z
[6] [6]
s ns ns ns ns ns ns ns ns ns ns 10 5 ns ns ns 5 ns ns ns ns ns ns ns ns ns ns 5 ns ns
CE HIGH to High Z [6] CE LOW to Power-up [7] CE HIGH to Power-down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z
[6] [7]
1
10 7 7 0 0 7 5.5 0 3 7
WE LOW to High Z [6] Byte Enable to End of Write
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 200 mV from steady state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR [11] tR
[12]
Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time
Conditions
Min 2
Typ[10]
Max
Unit V
VCC = 2 V , CE VCC - 0.2 V, VIN VCC - 0.2 V or VIN 0.2 V 0 tRC
25
mA ns ns
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0 V tCDR
VDR > 2 V
3.0 V tR
Switching Waveforms
Figure 3. Read Cycle No. 1 [13, 14]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) 50 s or stable at VCC(min.) 50 s. 13. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 14. WE is HIGH for read cycle.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Switching Waveforms
(continued) Figure 4. Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Figure 5. Write Cycle No. 1 (CE Controlled) [17, 18]
tWC ADDRESS
tSA CE
tSCE
tAW tPWE WE t BW BHE, BLE
tHA
tSD DATA I/O
tHD
Notes 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE transition LOW. 17. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Switching Waveforms
(continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [19, 20]
tWC
ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA I/O
tSD
tHD
tLZWE
Figure 7. Write Cycle No. 3 (BLE or BHE Controlled) [19]
tWC ADDRESS
tSA BHE, BLE tAW
tBW
tHA tPWE
WE tSCE CE tSD DATA I/O tHD
Notes 19. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read all bits Read lower bits only Read upper bits only Write all bits Write lower bits only Write upper bits only Selected, outputs disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C10612DV33-10ZSXI Package Diagram 51-85160 Package Type 54-Pin TSOP II (Pb-free) Operating Range Industrial
Ordering Code Definitions
CY
7
C
1 06 1 2 D
V33
XX
ZSX
I Temperature grade: I = Industrial ZS = TSOP II; X = Pb-free Speed: 10 ns Voltage range (3 V to 3.6 V) C9, 90 nm technology Single chip enable Data width x 16-bits 16-Mbit density Fast asynchronous SRAM family Technology: CMOS SRAM Cypress
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Package Diagrams
Figure 8. 54-Pin TSOP Type II
51-85160 *A
Acronyms
Table 1. Acronyms Used in this Document Acronym CE CMOS I/O OE SRAM SOJ TSOP VFBGA chip enable Complementary metal oxide semiconductor Input/output output enable Static random access memory Small Outline J-Lead Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description
Document Conventions
Units of Measure
Table 2. Units of Measure Symbol ns V A mA mV mW MHz pF C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure
Document Number: 001-49315 Rev. *B
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CY7C10612DV33
Document History Page
Document Title: CY7C10612DV33, 16-Mbit (1 M x 16) Static RAM Document Number: 001-49315 Rev. ** *A *B ECN No. 2589743 2718906 3128718 Orig. of Change VKN/PYRS VKN PRAS Submission Date 10/15/08 06/15/09 01/05/11 New datasheet Post to external web Template updates. Style changes. IO changed to I/O through out the document. Under Data Retention Characteristics on Page 6, "Typ" is associated with a new footnote # 10. Included ordering code definitions, Acronyms and units of measure tables. Updated package diagram from ** to *A. Description of Change
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(c) Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-49315 Rev. *B
Revised January 17, 2011
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